The present invention relates to a synchronizing signal detector circuit and, more particularly, to a synchronizing signal detector circuit free from the influence of noise and ghost and the variation of DC level of a composite synchronizing signal when detecting a predetermined synchronizing signal in the composite synchronizing signal.
An example of signal processings responsive to a synchronizing signal extracted from a composite synchronizing signal is horizontal and vertical synchronizing process in television receivers. It is necessary, for usual treatment of a video signal, that the horizontal and vertical synchronizing of transmitted video signal is carried out. In addition to functioning as horizontal and vertical synchronizing signals, the composite synchronizing signal also functions as a time reference signal which determines the start of various signal processes. When a ghost signal is superposed on a television signal, for example, the trailing edge of a vertical synchronizing signal is used as a reference for detecting a time delay of the ghost signal relative to a main video signal. In a system in which a television receiver detects character information superposed on the vertical retrace period of television signal, the trailing edge of vertical synchronizing signal detected from composite synchronizing signal is also used to determine the start timing of extraction of character information. As described above, the composite synchronizing signal functions as a time reference signal in addition to functioning as synchronizing signals. Therefore, it is important how phase jitter due to ghost and noise can be reduced when detecting a synchronizing signal in the composite synchronizing signal.
FIG. 1 shows a conventional synchronizing signal detector circuit in television receivers. This synchronizing signal detector circuit comprises a synchronizing signal separator circuit 10 for separating vertical synchronizing signal from a composite synchronizing signal, a pulse stretcher circuit 11 for stretching the pulse width of a pulse signal obtained through synchronizing signal separator circuit 10, and a counter circuit 12 for counting predetermined clock pulses to detect the pulse width obtained through pulse stretcher circuit 11.
The operation of conventional synchronizing signal detector circuit thus arranged will be now described. The composite synchronizing signal shown in FIG. 2A at an input terminal IN of synchronizing signal separator circuit 10 is applied to the base of a transistor Tr1 through a resistor R1 and a capacitor C1. A capacitor C2 for Miller integration is connected between the base and collector of transistor Tr1 so that an integrated composite synchronizing signal shown in FIG. 2B is obtained at the collector of transistor Tr1. The signal shown in FIG. 2B is applied to the base of a transistor Tr2 which is combined with a transistor Tr3 to form a differential pair. This differential pair of transistors Tr2 and Tr3 performs switching operation at a predetermined level of the signal shown in FIG. 2B. The switching level is determined by the base potential of transistor Tr3 which depends upon the resistance value of a variable resistor RS connected across a power supply. When transistor Tr2 is switched at a voltage level shown by a broken line in FIG. 2B, a pulse shown in FIG. 2C is obtained through the collector of transistor Tr2. This pulse shown in FIG. 2C is a vertical synchronizing signal but, as shown by V1 in FIG. 2C, a split may occur at the leading portion of the vertical synchronizing signal depending on the set value of switching level of transistor Tr3.
Using the pulse thus obtained and shown in FIG. 2C, digital treatment is carried out through pulse stretcher circuit 11 and counter circuit 12 to generate a vertical synchronizing signal having a predetermined phase.
The operation of pulse stretcher circuit 11 and counter circuit 12 will now be described. Pulse stretcher circuit 11 comprises cascade-connected JK flip-flops 13, 14, 15 and 16, and the output Q of final stage JK flip-flop 16 is fed back to the JK inputs of first stage JK flip-flop 13.
An output signal (FIG. 3A) of synchronizing signal separator circuit 10 is inverted by an inverter and applied, in such a form as shown in FIG. 3B, to the input terminal 11a of pulse stretcher circuit 11. Since JK flip-flops operate in negative logic, they are under reset condition during the time period when the pulse shown in FIG. 3B is low. When the period of low level shown in FIG. 3B has finished and the pulse then goes high, JK flip-flops are released from the reset condition. When JK flip-flops are released from the reset condition, they count clock pulses of a frequency sixty-four times the frequency fH of horizontal synchronizing signal which are applied to the input terminal of first stage JK flip-flop 13. Output waveforms of JK flip-flops 13, 14 and 15 are shown in FIGS. 3D, 3E and 3F respectively. As a result of this counting operation, when the output Q (FIG. 3G) of fourth stage JK flip-flop 16 goes high, the output Q (FIG. 3H) of JK flip-flop 16 coupled to the inputs of flip-flop 13 becomes low. As the result, the operation of counting clock pulses applied to pulse stretcher circuit 11 is stopped and the pulse shown in FIG. 3H is obtained through the output Q of JK flip-flop 16. As apparent from the above, pulse stretcher circuit 11 stretches the pulse width of pulse (FIG. 3B) by a period of time during which JK flip-flops 13 to 16 count clock pulses by a predetermined value starting from the trailing edge of pulse. This pulse (FIG. 3B) stretching period is about 8 .mu.sec since the frequency of clock pulses is made sixty-four times the frequency (15.75 kHz) of horizontal synchronizing signal. Therefore, the pulse stretching circuit stretches the pulse width of inverted pulse of output pulse of synchronizing signal separator circuit 10 for about 8 .mu.sec.
The counter circuit 12 comprises cascade-connected JK flip-flops 17, 18, 19 and 20. Each of JK flip-flops is reset by a signal which is the inverse of the output signal of the output Q of final stage JK flip-flop 16 in pulse stretcher circuit 11. Namely, each of JK flip-flops 17, 18, 19 and 20 is kept released from its reset condition during the period that the output Q of JK flip-flop 16 shown in FIG. 3H is high. During this period the counter circuit 12 counts clock pulses .alpha. applied to the first stage JK flip-flop 17. It is detected by counting clock pulses .alpha. by a predetermined value that an incoming pulse is a vertical synchronizing signal. A pulse which serves as a phase reference of the vertical synchronizing signal is generated by a pulse generator circuit (not shown) responsive to this detection.
Namely, the conventional synchronizing signal detector circuit stretches for about 8 .mu.sec the pulse width of a vertical synchronizing signal separated by synchronizing signal separator circuit 10 to thereby fill the split portion caused by noise in the vertical synchronizing signal. The counter circuit 12 starts to count clock pulses .alpha. starting from the leading edge of vertical synchronizing signal in which the influence due to noise is reduced. When the counter counts clock pulses .alpha. by the predetermined value at this time, the incoming pulse is detected to be a vertical synchronizing signal. The pulse which serves as the reference phase of the vertical synchronizing signal is generated through the pulse generator circuit (not shown) responsive to output of counter circuit 12, thus allowing a synchronizing signal to be extracted.
However, the conventional synchronizing signal detector circuit has following drawbacks.
A synchronizing signal extracted from the composite synchronizing signal is used as a synchronizing signal by which signal treatment is performed synchronizing with a transmitted signal, and also as a reference time signal by which various signal treatments are performed. It is therefore desirable that the synchronizing signal is stable both in frequency and phase. In the case where a vertical synchronizing signal is extracted from the composite synchronizing signal of a television signal for achieving vertical synchronization or generating a reference time to extract character information inserted in the vertical retrace period, it is necessary to consider the influence due to noise and ghost signal. When a negative ghost is superposed on a television signal, the synchronizing signal portion comes to have a stepped waveform as shown in FIG. 4A. The DC level of synchronizing signal portion also varies this time and the vertical synchronizing signal is separated at a DC level different from that set by the variable resistor in synchronizing signal separator circuit 10. Therefore, the output of synchronizing signal separator circuit 10 has splits at the leading edge portion of pulse as shown in FIG. 4B. If the period of this split portion lasts about 8 .mu.sec, this split portion cannot be filled by pulse stretcher circuit 11. Therefore, the counter circuit 12 starts to count clock pulses .alpha. not starting from the leading edge of pulse separated through synchronizing signal separator circuit 10 but from the trailing edge of split portion. This causes counter circuit 12 to perform such a malfunction that a vertical synchronizing signal cannot be detected.
When noise is mixed in the vertical synchronizing signal portion as shown in FIG. 4C, the output signal of synchronizing signal separator circuit 10 has, at the leading edge portion thereof, split portions caused by the influence of noise as shown in FIG. 4D. Similarly to the case where ghost signal is superposed, correct vertical synchronizing signal cannot be extracted due to the malfunction of counter circuit 12 relating to its counting start.
As described above, the conventional synchronizing signal detector circuit causes malfunction when a ghost signal is superposed on the main signal or noise is mixed in it. This is because a synchronizing signal is detected using its leading edge portion as a reference notwithstanding its leading edge portion is more easily influenced by ghost signal and noise than its trailing edge portion.